VLSI design training and Compute-in-Memory consulting
Classroom-tested VLSI instruction and CIM research support — for training institutes running batches, colleges needing guest faculty, and engineers preparing for GATE.
How we can work together
Guest / Adjunct Teaching
Evening or weekend lecture slots for VLSI, digital design, or semiconductor fundamentals at your institute or college.
VLSI Training Batches
Structured Verilog/VHDL and ASIC-flow training for working professionals or final-year students.
GATE ECE Mentoring
Small-group or one-to-one mentoring focused on the VLSI portion of GATE ECE.
Research Consulting
Review and feedback on VLSI/CIM research work, thesis chapters, or paper drafts.
Subject areas covered
VLSI & Digital Design
CMOS fundamentals, combinational & sequential design, timing analysis, and the standard ASIC/FPGA design flow.
Compute-in-Memory
Memory-centric architectures for AI acceleration — SRAM/ReRAM-based crossbar arrays, analog and digital CIM tradeoffs.
Verilog & VHDL
RTL design and verification, from first-principles coding style to synthesis-aware design practices.
GATE ECE — VLSI
Focused mentoring on the VLSI section of GATE ECE, consistently one of the highest-difficulty, highest-weightage topics.
M.Tech Coursework
Semester-length or module-based teaching support for postgraduate VLSI and semiconductor courses.
Research Consulting
Literature review, methodology feedback, and technical review for VLSI/CIM research work and papers.
Writing on Compute-in-Memory
What is Compute-in-Memory, really?
In a conventional processor, data is fetched from memory, moved to a compute unit, processed, then moved back. That movement, not the computation itself, is often what costs the most time and energy. Compute-in-Memory rethinks this by performing certain operations — commonly matrix-vector multiplication — directly within the memory array. The result isn't a faster processor; it's an architecture that avoids needing to move as much data in the first place.
Why CIM matters for AI hardware
Neural network inference is dominated by matrix-vector multiplications, run repeatedly against weights stored in memory. On conventional hardware, that means constant traffic between memory and compute. CIM designs map those weights directly onto a memory array — often a crossbar of resistive or SRAM cells — so the multiplication happens as a physical property of the array itself. This is a big part of why CIM has become a serious research direction for edge-AI and low-power inference chips.
A roadmap into VLSI, for M.Tech & GATE aspirants
Most students hit VLSI as a wall of unfamiliar terms before they see how it fits together. A workable order: start with CMOS device behavior, then combinational and sequential logic design, then move into a hardware description language (Verilog or VHDL), and only after that into timing, synthesis, and the physical design flow. Skipping ahead to tools before the fundamentals is the most common reason students get stuck.
Who's behind this
This work is led by Bharat Singh Choudhary, who spent over ten years as an Assistant Professor teaching digital design and VLSI at the M.Tech level before returning to full-time research. He's currently engaged in active research on Compute-in-Memory (CIM) — architectures that perform computation directly inside memory arrays, a direction that's become central to modern AI and edge-computing hardware. That combination — classroom experience plus active research — is what shapes the training and consulting offered here.
- RoleVLSI Design Educator & Researcher
- Research focusCompute-in-Memory (CIM)
- Prior roleAssistant Professor, M.Tech
- Teaching experience10+ years
- Contactbrt.bharat@gmail.com
Get in touch
Teaching, training, or research collaboration?
Reach out with your institute, batch size, or research topic, and a good time to connect. Evening and weekend slots generally work best.